VIA Technologies x86 Microprocessors
Product Engineer to VP
1999-2011
Elevating from a position of Sr. Product Engineer of Manufacturing & Product Engineering, all areas of responsibility and development of complex semiconductor manufacturing, test, and planning were successfully executed.
Sr. Product Engineer
Identified >15% yield loss due to cache failures by developing custom software to analyze GB of data and identify patterns that correlated to circuit and physical topography causes resulting in TSMC design rule change, yield recovery, and higher average device speed grading.
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Director of Engineering
Conceived, designed, prototyped, and produced burn-in, system test, and other custom test infrastructure for x86 microprocessors that were less expensive but more capable than commercial alternatives.
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VP of Manufacturing & Product/Test Engineering
Improved team efficiency and created full remote monitoring and control of offshore test infrastructure and production logistics.